Periodic scheduling of marked graphs using balanced binary words

This report presents an algorithm to statically schedule live and strongly connected Marked Graphs (MG). The proposed algorithm computes the best execution where the execution rate is maximal and place sizes are minimal. The proposed algorithm provides transition schedules represented as binary words. These words are chosen to be balanced. The contributions of this paper is the proposed algorithm itself along with the characterization of the best execution of any MG.Comment: No. RR-7891 (2012

Normal Forms and Equivalence of K-periodically Routed Graphs

We introduce K-periodically Routed Graphs, which are extensions of Marked Graphs with routing nodes, governed by ultimately periodic binary sequences. We study data relations and dependencies, as well as equational transformations of the network topology. We show the existence of expanded normal forms. We prove that some transformations preserve external flow equivalence. Issues arising from internal flow interleavings and permutations are also tackled

Correctness Issues on MARTE/CCSL constraints

International audienceThe UML Profile for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities offered by MARTE, much less on available verification techniques. The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analysis on MARTE models.This work relies on a state-based semantics for CCSL to establish correctness properties on MARTE/CCSL specifications. We propose and compare two different techniques to build the state-space of a specification. One is an extension of some previous work and is based on extended finite state machines. It relies on integer linear programming to solve the constraints and reduce the state-space. The other one is based on an intentional representation and uses pure Boolean abstractions but offers no guarantee to terminate when the specification is not safe.The approach is illustrated on one simple example where the architecture plays an important role. We describe a process where the logical description of the application is progressively refined to take into account the execution platform through allocation

MARTE: A Profile for RT/E Systems Modeling, Analysis (and Simulation?)

The original publication is available from ACM Digital Library (http://portal.acm.org/citation.cfm?id=1416222.1416271)International audienceAs its name promises, the Unified Modeling Language (UML) provides a collection of diagrammatic modeling styles. To the early class/objects and use-case diagrams were almost immediately added state-, activity-, collaboration-, and component diagrams. All these modeling views, required for structural and behavioral representations of systems, were then progressed to further detailed expressivity. Provision for domain- specific specializations was made under the form of profiles. Somehow this goal of being rather universal and extendible discarded the possibility of UML to adopt too strict and precise a semantics; as users were generally to define and refine it in their stereotyped profiles anyway. As a result, even the little execution semantics there is in the standard is often not considered in such specializations. We tackled the general issue of defining a broadly expressive Time Model as a sub-profile of the upcoming OMG Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE), currently undergoing finalization at OMG. The goal is to provide a generic timed interpretation, on which timed models of computation and timed simulation semantics could be built inside the UML definition scope, instead of as part of the many external proprietary profiles. The MARTE time library can be used as the basis for the definition of a UML real-time simulator

Refining cellular automata with routing constraints

A cellular automaton (CA) is an infinite array of cells, each containing the same automaton. The dynamics of a CA is distributed over the cells where each computes its next state as a function of the previous states of its neighborhood. Thus, the transmission of such states between neighbors is considered as feasible directly, in no time. When considering the implementation of a cellular automaton on a many-cores System-on-Chip (SoC), this state transmission is no longer abstract and instantaneous, but has to follow the interconnection medium of the SoC. It is usually a grid or a mesh matching the underlying topology of the CA but finite. In order to consider such constraints at a higher level, we propose a refinement of the classical model of CA where the topology is considered as the communication medium. If the state of a cell depends on its neighbors up to a certain distance, then a given state must be broadcasted to all its neighbors at the same distance, as they all require it to compute their next state. It means routing and duplicating the state in the topology. We study the routing patterns needed to efficiently implement such state broadcasting algorithm. We provide a solution by which each router can locally predict where to redirect the states to correctly and efficiently implement this broadcasting algorithm.Un automate cellulaire (AC) est un tableau infini de cellules, chacune contenant le même automate. La dynamique d'un AC est distribuée entre les cellules, chacune calcule son prochain état comme une fonction des états de ses voisins. Donc, la transmission d'un état entre deux cellules est donc considérée comme faisable directement et instantanément. Quand on s'intéresse à l'implémentation d'un AC sur un système sur puce à plusieurs cores, on ne peut plus considérer la transmission d'un état comme une action abstraite et instantanée. Cette transmission doit suivre le medium d'interconnexion du système sur puce. Ce dernier est habituellement une grille ou un mesh (grille dans laquelle les extrémités opposées sont connectées) correspondant à la topologie logique de l'AC mais finie. Afin de prendre en compte la notion de medium d'interconnexion à un niveau d'abstraction supérieur, par rapport à l'implémentation, nous proposons un raffinement du modèle classique des AC dans lequel la topologie est considérée comme le medium d'interconnexion. Si l'état d'une cellule dépend de son entourage jusqu'à une certaine distance, alors cet état doit être diffusé à tous les voisins jusqu'à cette même distance puis ce que chacun d'eux en a besoin pour calculer son nouvel état. Cela signifie router et diffuser l'état en question dans la topologie. Nous étudions le schéma de routage nécessaire pour mettre en oeuvre efficacement cet algorithme de diffusion d'état. Dans cette solution, chaque router peut localement prédire où envoyer les états en transit afin de garantir la justesse de l'algorithme

Deleterious effects of xanthine oxidase on rat liver endothelial cells after ischemia/reperfusion

AbstractPrevious studies have demonstrated that reactive oxygen species are involved in ischemic injury. The present work was undertaken to determine in vivo the role of xanthine oxidase in the oxygen free radical production during rat liver ischemia and to examine the activity of antioxidant enzymes (superoxide dismutase, catalase and glutathione peroxidase) during the same period. Our results indicate a 4-fold increase in xanthine oxidase activity between 2 and 3 hours of normothermic ischemia, in parallel with a decrease in cell viability. Moderate hypothermia delays both events. Under the same conditions, the activity of oxygen radical scavenging enzymes remains unchanged. Moreover, we have compared in vitro the susceptibility of isolated liver cells to an oxidative stress induced by O2·−, H2O2 and OH. Our results reveal that endothelial cells are much more susceptible to reactive oxygen species than hepatocytes, probably because they lack H2O2-detoxifying enzymes. These findings suggest that xanthine oxidase might play a major role in the ischemic injury mainly at the level of the sinusoidal space where most endothelial cells are located

Modeling of Immediate vs. Delayed Data Communications: from AADL to UML MARTE

The original publication is available at http://www.ecsi-association.org/ecsi/main.asp?l1=library&fn=def&id=265International audienceThe forthcoming OMG UML Profile for Modeling and Analysis of Real-Time Embedded systems (MARTE) aims, amongst other things, at providing a referential Time Model subprofile where semantic issues can be explicitly and formally described. As a full-size exercise we deal here with the modeling of immediate and delayed data communications in AADL. It actually reflects an important issue in RT/E model semantics: a propagation of immediate communications may result in a combinatorial loop, with ill-defined behavior; introduction of delays may introduce races, which have to be controlled. We describe here the abilities of MARTE in this respect

The FCTOOLS User Manual (Version 1.0)

We describe a set of modular extensions to our Auto/Graph verification toolset for networks of communicating processes. These software additions operate from a common file exchange format for automata and networks, called {\sc fc2}. Tool functionalities comprise graphical depiction of objects, global model construction from hierarchical descriptions, various types of model reductions and of verification of simple modal properties by observers, counterexample production and visualisation. We illustrate typical verification sessions conducted on usual academic examples: dining philosophers, mutual exclusion algorithms and round-robin schedulers. Based on previous experience of drastic state explosion problems we aim here at efficiency in implementation. We use both explicit representation techniques and implicit techniques such as {\sc BDD}s, with functional overlap at places

Higher-level synchronizing devices in Meije-SCCS

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